RT7320 ? ds7320-00 september 2013 www.richtek.com 1 ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. high voltage programmable constant-current led driver general description the RT7320 is a simple and robust constant-current regulator designed to provide a cost-effective solution for driving high-voltage leds in led lamp applications. the wide input voltage range (up to 400v) allows flexible led string design to operate with 110v rms or 220v rms ac input voltage. the RT7320 allows users to set the regulated current level by connecting the pins from i1 to i5 for various led lamps. parallel led strings operation is possible with right regulated current setting on the RT7320. in addition, the RT7320 also provides a thermal regulation protection, instead of traditional thermal shutdown, to suppress the rise of ic junction temperature and prevent led lamps from flicker. simplified application circuit applications z high-voltage led lamps z high-voltage sinking current regulator marking information features z z z z z programmable regulated current : 2.8ma to 78.3ma z z z z z ac input voltage : 90 to 130v rms or 200 to 240v rms z z z z z thermal regulation protection z z z z z minimized start-up time (<10ms) z z z z z easy emi solution z z z z z minimized bom cost and space required z z z z z small sop-8 (exposed pad) package z z z z z rohs compliant and halogen free ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. RT7320 lead plating system g : green (halogen free and pb free) package type sp : sop-8 (exposed pad-option 2) pin configurations (top view) sop-8 (exposed pad) out nc gnd i1 i5 i4 i2 i3 gnd 2 3 4 5 6 7 8 9 gnd i4 i3 i2 RT7320 out c1 i1 i5 + ac RT7320 gspymdnn RT7320gsp : product number ymdnn : date code
RT7320 2 ds7320-00 september 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 out output of the constant-current regulator. a programmable regulated current, flowing into this pin, drives high-voltage leds connected between this pin and the rectified voltage. 2 nc no internal connection. 3, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 4 i1 current setting input. if this pin is directly connected to gnd, the regulated current increases 2.8ma (typical). 5 i2 current setting input. if this pin is directly connected to gnd, the regulated current increases 5.5ma (typical). 6 i3 current setting input. if this pin is directly connected to gnd, the regulated current increases 10ma (typical). 7 i4 current setting input. if this pin is directly connected to gnd, the regulated current increases 20ma (typical). 8 i5 current setting input. if this pin is directly connected to gnd, the regulated current increases 40ma (typical). function block diagram i5 gnd out m1 voltage regulator i4 + - error amplifier i3 i2 i1 i 5 i 4 i 3 i 2 i 1 40ma 20ma 10ma 5.5ma 2.8ma r5 = r r4 = 2r r3 = 4r r2 = 8r r1 = 16r thermal regulation protection v ref
RT7320 3 ds7320-00 september 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation constant-current regulator the constant-current regulator in the RT7320 consists of an output high-voltage mosfet (m1), programmable current-sense resistors (r1 to r5), an error amplifier and a reference voltage (v ref ). the error amplifier, designed with high dc gain, compares the current signal (v cs ) on the current-sense resistors and the v ref to generate an amplified error signal. the error signal regulates the output mosfet to control the sinking current on the out pin at the programmed current level. in addition, the operating out voltage (v out ) must be higher than the minimum out voltage (v out_min ). otherwise, the output current might not be regulated at the programmed level (i out_set ). the v out_min is approximately calculated by the following equation : v out_min = 3000 x i out_set 2 + 4 (v) thermal regulation protection when a led lamp operates in high ambient temperature conditions, it needs a thermal protection to limit the temperatures for protecting led lamps and ensuring system reliability. the RT7320 provides a thermal regulation protection, instead of traditional thermal shutdown, to suppress the rise of temperatures. when the ic junction temperature rises above 125 c (typ.), this function starts to gradually reduce the regulated led current, depending on the rise of the junction temperature. meanwhile, the system power dissipation is also reduced. finally, the temperatures in the system will be well controlled and enter their steady-state. the function can achieve both of the two targets : to protect led lamps and to prevent them from flicker.
RT7320 4 ds7320-00 september 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. electrical characteristics (t a = 25 c, unless otherwise specification) absolute maximum ratings (note 1) z out to gnd --------------------------------------------------------------------------------------------------------------- ? 0.3v to 250v z i1, i2, i3, i4, i5 to gnd --------------------------------------------------------------------------------------------------- ? 0.3v to 5v z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) -------------------------------------------------------------------------------------------------- 3.44w z package thermal resistance (note 2) sop-8 (exposed pad), ja --------------------------------------------------------------------------------------------- 29 c/w sop-8 (exposed pad), jc -------------------------------------------------------------------------------------------- 2 c/w z junction temperature ---------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------ 260 c z storage temperature range ------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) --------------------------------------------------------------------------------------------- 2kv mm (ma chine model) ---------------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z input dc voltage, v out -------------------------------------------------------------------------------------------------- 0v to 100v z input current, i out -------------------------------------------------------------------------------------------------------- 2.8ma to 78.3ma z ambient temperature range ------------------------------------------------------------------------------------------- ? 40 c to 85 c z junction temperature range ------------------------------------------------------------------------------------------- ? 40 c to 125 c parameter symbol test conditions min typ max unit out section out regulated current level-1 i 1 v ou t = 30v, i1 = gnd 2.66 2.8 2.94 ma out regulated current level-2 i 2 v ou t = 30v, i2 = gnd 5.225 5.5 5.775 ma out regulated current level-3 i 3 v ou t = 30v, i3 = gnd 9.5 10 10.5 ma out regulated current level-4 i 4 v out = 30v, i4 = gnd 19 20 21 ma out regulated current level-34 i 34 v out = 30v, i3 = i4 = gnd 28.5 30 31.5 ma out regulated current level-5 i 5 v out = 30v, i5 = gnd 38 40 42 ma
RT7320 5 ds7320-00 september 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit gnd i3 i2 RT7320 out c1 i1 1 4 3, 9 (exposed pad) 8 6 i5 5 + ac i4 7
RT7320 6 ds7320-00 september 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics output current vs. out voltage 0 5 10 15 20 25 30 35 40 45 50 0 25 50 75 100 125 150 175 200 out voltage (v) output current (ma ) i = 10ma i = 20ma i = 30ma i = 40ma thermal regulation protection 0 5 10 15 20 25 30 35 40 45 -40 -20 0 20 40 60 80 100 120 140 160 180 temperature (c) i s1 (ma)
RT7320 7 ds7320-00 september 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 6. derating curve of maximum power dissipation application information input capacitor input capacitor (c1) determines the resulted minimum dc voltage and hold-up time. definition of the parameters : vi min : minimum line input (vrms) f line : line frequency (hz) vdc valley : minimum dc voltage for the system dc voltage at minimum line voltage vdc min_pk is given as 0.0 0.6 1.2 1.8 2.4 3.0 3.6 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) package, the thermal resistance, ja , is 29 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (29 c/w) = 3.44w for sop-8 (exposed pad) package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. min_pk min vdc 2 vi (v) = calculation of charging duty d ch each half-line cycle valley min_pk vdc 11 dch asin 2vdc ?? =? ?? ?? ?? after the selected minimum dc voltage, the minimum input capacitance is obtained by the following equation : 22 min_pk valley line pin (1 dch) c1_min (f) (vdc vdc ) f ? = ? output current setting the typical regulated currents are calculated by the following equation : iout = i1 (if i1 = gnd) + i2 (if i2 = gnd) + i3 (if i3 = gnd) + i4 (if i4 = gnd) + i5 (if i5 = gnd)
RT7320 8 ds7320-00 september 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations ` the thermal resistance ja of sop-8 (exposed pad) is determined by the package design and the pcb design. however, the package design had been designed. if possible, it's useful to increase thermal performance by the pcb design. the thermal resistance ja can be decreased by adding a copper under the exposed pad of sop-8 (exposed pad) package. the exposed pad can be connected the ground or an isolated plane on the pcb. ` the used current setting pins (i1 to i5) must be directly connect to the gnd pin with shortest copper paths. not-used current setting pins (i1 to i5) must be kept open.
RT7320 9 ds7320-00 september 2013 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138
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